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Technology
- The purpose of an IC “package” is to provide interconnection and protection for semiconductor die. Despite popular preconceptions, packaging is a major cost factor in the ultimate price of an IC – ranging on average from 15% to 17%, depending on the industry.
- Generally speaking, technology evolution on the die has dramatically outpaced the evolution of its packaging. Conventional packaging techniques, such as wire bonding, result in packages that have large footprints, low performance, and high cost relative to the dies packaged within them.
- “Wafer level packaging,” or WLP, changes the equation dramatically. While traditionally the industry packaged each individual die unit after wafer slicing, WLP technologies accomplish IC packaging at the wafer level. A dramatically smaller (true chip size) and thinner footprint results.
- WLP enhances performance by reducing interconnect distances, power consumption, and thermal generation. Cost is also dramatically decreased since higher yields are achieved, and expensive manufacturing processes are consolidated or eliminated entirely.
- WLP is “green,” since manufacturing complexity is reduced and RoHS plastics are eliminated.
- The wafer level packaging techniques provided by the Chip Scale Portfolio include “Wrap Around,” “Through Silicon Via” or (TSV), and “Flip Chip.”
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